The present invention relates generally to semiconductor memory designs and more particularly to the design of semiconductor memories with refreshing cycles.
A constant voltage stress leads to rapid degeneration of transistor parameters, such as threshold voltage and source-drain current. This phenomenon is known as negative bias temperature instability (NBTI) and is the result of charge buildup at an interface between silicon and silicon dioxide due to the influence of negative voltages on the gate electrode of metal-oxide-semiconductor (MOS) structures. The NBTI effect is more severe for P-channel MOS (PMOS) transistors than the N-channel MOS (NMOS) transistors due to the presence of holes in the PMOS inversion layer that react with the oxide states. NBTI degrades the reliability of the PMOS transistor due to the change in threshold voltage and the degradation increases at elevated temperatures and is exponential with electric field across the gate oxide of the PMOS. However, if the stress is periodically interrupted (AC stress), as it would during normal operation, the degradation may be significantly reduced, extending the projected lift-time of the MOS transistors.
A conventional six-transistor static random access memory (SRAM) cell consists of two PMOS transistors and four NMOS transistors. With any data storage in the SRAM cell the effects of NBTI degrade one of the PMOS transistors. If the same data is stored in the SRAM memory cell for an extended period of time, then there is substantial degradation on that PMOS transistor. During the operation of the SRAM, even if the data read and write operations are performed frequently with different data contents, there is a good possibility that some of the SRAM memory cells stored the same high state or low state for an extended period of time. These non-refreshed memory cells will have higher degradation in one of their PMOS transistors due to NBTI that will decrease the reliability of that SRAM cell, as well as the life-time of the entire SRAM memory.
Accordingly, there is a need for a design that can reduce the NBTI degradation of the PMOS transistors through alternating the stress on the PMOS transistors.